t81-foundation

Research Synthesis & Decision Report — Ternary Research Closure and Next-Hypothesis Selection

Document ID: docs/research/TERNARY_RESEARCH_CLOSURE_AND_NEXT_HYPOTHESIS.md Date: April 2026 Status: Complete / Final Research Synthesis Authors: Jules (Software Engineer — Adversarial Synthesis) Target Repository: T81 Foundation (t81dev/t81-foundation) Associated Sequence: PRs #544–#549 (Ternary Arithmetic, Radix Comparison, Packed Ternary MatVec, SIMD Decoders, Cross-Architecture Break-Even) Experimental Artifacts: experiments/radix_comparison/, experiments/packed_ternary_matvec/

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Executive Summary

This report concludes the ternary CPU arithmetic and inference research sequence executed in PRs #544 through #549. Through a rigorous evidence reconstruction, adversarial audit, prior-art contextualization, and experimental freeze, we establish the empirical boundary of CPU ternary execution and select the next research hypothesis for the T81 Foundation.

Key Operational Decisions

1. CPU Ternary Kernel Optimization Frozen (STOP): Further optimization of software CPU ternary kernels (scalar, SWAR, LUT, AVX2 VPSHUFB, ARM NEON vqtbl1_s8) is formally frozen. Custom CPU ternary bit manipulation cannot compete with native 8-bit/32-bit SIMD vector execution on general-purpose binary ALUs.
2. Inference Standardization: Standardize CPU-based ternary model inference ($W \in {-1, 0, 1}$) on native byte-aligned INT8 / FP16 SIMD execution pipelines (e.g., GGML / llama.cpp vector dequantization), using 2-bit packing exclusively as a memory storage and transmission format.
3. Next Hypothesis Selected: Select Candidate 3: Deterministic Execution & Canonical Provenance Verification in Policy-Gated AI Runtimes (RFC-0028 / RFC-0030 / Axion) as the single bounded 30-day research objective.

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Phase 1 — Evidence Reconstruction & Claim/Evidence Ledger

A comprehensive audit of the source changes, CTest targets, benchmark reports, and CI execution artifacts across PRs #544–#549 yields the following claim/evidence ledger, categorized into six distinct evidential tiers.

Claim / Evidence Matrix (PRs #544–#549)

Category	Claim / Statement	Empirical Status	Source Artifacts	Verified Reality / Boundary Conditions
1. Mathematical Proofs	Uniqueness of Balanced Ternary representation	CONFIRMED	TERNARY_ARITHMETIC_AND_RADIX_COMPARISON.md	Proved by induction on $	V	$. Digit sequence $d_i \in {-1,0,1}$ is strictly unique for every integer $V \in \mathbb{Z}$.
	Radix-3 Redundant Signed-Digit (RSD) Zero Uniqueness	CONFIRMED	TERNARY_ARITHMETIC_AND_RADIX_COMPARISON.md	Proved $V=0 \implies d_i=0 \, \forall i$ in $D={-2..2}$ ($d_0 \equiv 0 \pmod 3 \implies d_0=0$). Corrects initial PR #544 proof error.
	Non-Zero RSD Equality Testing Cost	CONFIRMED	TERNARY_ARITHMETIC_AND_RADIX_COMPARISON.md	Non-zero values have redundant representations (e.g., $1 = \langle 1 \rangle_3 = \langle 1, -2 \rangle_3$). Determining $A == B$ requires $O(N)$ canonicalization.
	64-Bit Integer Trit / Byte Requirement	CONFIRMED	TERNARY_ARITHMETIC_AND_RADIX_COMPARISON.md	$3^{40} < 2^{64} < 3^{41} \implies 41 \text{ trits}$ needed ($11 \text{ bytes}$ at 2 bits/trit), correcting PR #544’s 40-trit / 10-byte claim.
2. Implemented Algorithms	Stack-backed Radix-81 tryte addition (std::array)	CONFIRMED	experiments/radix_comparison/radix_comparison.hpp	Fixed-width 11-tryte array addition reduces latency from $105.34\text{ ns}$ down to $11.70\text{ ns}$ by removing heap allocation.
	2-bit AVX2 SIMD MatVec (matvec_ternary_2bit_avx2)	CONFIRMED	experiments/packed_ternary_matvec/matvec_experiment.hpp	VPSHUFB nibble-parallel lookup table decoding eliminates scalar shift/mask instructions, achieving $12.91\text{ GFLOP/s}$ on $4096^2$.
	ARM64 NEON candidate (matvec_ternary_2bit_neon)	CONFIRMED	experiments/packed_ternary_matvec/matvec_experiment.hpp	Table lookup via vqtbl1_s8 implemented, but multi-instruction vzip/unpacking limits throughput under emulated conditions.
3. Correctness Tests	Oracle correctness across 18 matrix shapes & 7 patterns	CONFIRMED	t81_packed_ternary_matvec_oracle_test	$100\%$ pass across 126 shape/pattern combinations against double-precision reference (matvec_oracle_f64).
	Invalid 2-bit code policy ($0\text{x}02 \to 0$)	CONFIRMED	matvec_experiment.hpp	Code $10_2$ ($0\text{x}02$) decodes safely to $0$ across all kernels without faulting or contaminating accumulations.
4. Reproducible Benchmarks	Fixed-array Radix-81 add ($11.7\text{ ns}$) vs Binary ALU ($1.1\text{ ns}$)	CONFIRMED	t81_radix_comparison_test	Grouping 4 trits into Base-81 trytes speeds up software ternary add by $2.77\times$, but binary 64-bit ALU remains $10.6\times$ faster.
	2-bit AVX2 MatVec ($12.91\text{ GFLOP/s}$) vs INT8 AVX2 ($17.15\text{ GFLOP/s}$)	CONFIRMED	t81_packed_ternary_matvec_oracle_test	AVX2 2-bit SIMD kernel reaches $75.3\%$ of INT8 AVX2 speed on DRAM-bound $4096^2$ workloads while saving $75\%$ weight footprint.
5. Emulated Hardware Results	ARM64 NEON MatVec throughput	CAVEATED	t81_packed_ternary_matvec_arm64_qemu_test	Executed via qemu-aarch64 user emulation. Reflected QEMU JIT translation overhead rather than physical ARM silicon cycle times.
6. Speculative Extrapolations	“2-bit packing provides faster CPU MatVec execution than INT8”	FALSIFIED	Cross-architecture break-even audit	On general binary CPUs, 2-bit bit-shuffle decode instruction tax offsets memory bandwidth savings across all cache tiers.
	“4-trit limb BigInt suffers a $102\times$ multiplication penalty”	CONTEXTUALIZED	T81BigInt repo inspection	Strawman 4-trit limb is $102\times$ slower; actual T81BigInt implementation uses 27-trit limbs ($3^{27}$, 42.8 bits), incurring only a $2.23\times$ penalty.

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Phase 2 — Audited Research Conclusions & Document Corrections

An audit of the historical research documentation across PRs #544–#549 reveals several initial errors, overstatements, and analytical gaps that require formal correction.

1. Mathematical Example & Proof Corrections

• PR #544 RSD Counterexample Error: The proof in PR #544 attempting to demonstrate non-unique zero in Radix-3 RSD cited $\langle +1, -3 \rangle$ (using $-3 \notin {-2..2}$) and claimed $1 \cdot 3^3 + (-2) \cdot 3^2 + (-1) \cdot 3^1 + 0 = 0$ (miscalculating $(-1) \cdot 3^1 = -3$, yielding $27 - 18 - 3 = 6 \neq 0$). PR #545 provided the rigorous proof that $V=0$ is strictly unique in $D={-2..2}$.
• 64-Bit Domain Range Correction: PR #544 claimed 40 trits (10 bytes) covers 64-bit signed integers. In reality, $(3^{40}-1)/2 = 6.078 \times 10^{18} < \text{INT64_MAX} = 9.223 \times 10^{18}$. Full signed 64-bit coverage requires 41 trits ($11\text{ bytes}$ at 2 bits/trit).

2. Overstated Performance & Memory Bandwidth Claims

• Initial On-the-Fly Decoding Claims: Early claims suggested on-the-fly 2-bit decoding would accelerate MatVec over INT8 by reducing DRAM reads. Audits demonstrated that scalar/SWAR on-the-fly decoding is up to $69\times$ slower than INT8 AVX2 ($0.28\text{ GFLOP/s}$ vs $19.35\text{ GFLOP/s}$) due to loop masking and branch mispredictions.
• SIMD Capping Ratio: Even with the VPSHUFB SIMD decoder (matvec_ternary_2bit_avx2), execution speed caps at $12.91\text{ GFLOP/s}$ ($75.3\%$ of INT8 AVX2). The $4\times$ memory footprint reduction saves DRAM read bandwidth ($1.63\text{ GB/s}$ vs $8.59\text{ GB/s}$), but the ratio of bit-shuffle decode instructions to arithmetic accumulation instructions inside the vector pipeline prevents 2-bit packed ternary from beating INT8 on execution speed.

3. QEMU Emulation vs Physical Hardware Contextualization

• Benchmark metrics for t81_packed_ternary_matvec_arm64_qemu_test were collected using qemu-aarch64 8.2.2 user emulation on an x86_64 host.
• Correction: QEMU user emulation measures software dynamic translation latency, host OS scheduling, and virtualized vector instructions. These numbers validate algorithmic correctness and instruction sequence validity, but must not be presented as physical ARM silicon throughput or cycle efficiency.

4. Single-Use vs Pre-Packed Execution Path Separation

• Benchmarks comparing single-use execution (packing weights + running MatVec) against pre-packed repeated inference revealed a massive path divergence:
  • Weight Packing Cost ($W_{\text{trits}} \to W_{\text{packed_2bit}}$): $102.69\text{ ms}$ for $4096^2$.
  • Pre-Packed Repeated AVX2 MatVec Pass: $2.59\text{ ms}$.
  • Single-Use End-to-End Latency: $209.18\text{ ms}$.
• Correction: Comparative research must strictly separate off-line weight packing (compilation time) from pre-packed inference execution. Single-use packing overhead renders on-the-fly ternary packing non-viable for single-token latency.

5. Prior-Art Analysis

• Avizienis (1961): “Signed-Digit Number Representations for Fast Parallel Addition” established $O(1)$ carry-free parallel addition in signed-digit representations, but noted the mandatory $O(N)$ canonicalization cost for equality and zero testing.
• Setun Computer (Brusentsov et al., Moscow State University, 1958): Built hardware balanced ternary computer using magnetic core logic (-1, 0, +1). Proved naturally signed arithmetic and high hardware reliability, but failed to achieve commercial dominance against binary CMOS scaling.
• BitNet b1.58 (Ma et al., Microsoft Research, 2024): 1.58-bit LLM quantization ($W \in {-1, 0, 1}$). Demonstrated that 1.58-bit ternary weights achieve FP16 quality while drastically reducing DRAM weight memory footprint, but relies on dequantizing/unpacking into 8-bit/16-bit registers or matrix hardware for execution.
• llama.cpp / ggml (Gerganov et al., 2023–2024): SIMD vector dequantization (AVX2 VPSHUFB, ARM NEON tbl) for low-bit quantization (IQ2_XXS, Q2_K, IQ1_S). Demonstrated that lookup-table vector dequantization into INT8/FP16 registers maximizes memory-bandwidth efficiency for LLM token generation (batch size 1), while raw arithmetic remains in binary SIMD ALUs.

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Phase 3 — Frozen Experiment Status & Preservation Register

Preservation Status: FROZEN / STOP

All experimental software implementations, CTest targets, and benchmark harnesses developed in PRs #544–#549 are preserved in the repository as reproducible historical research baselines. No further engineering effort will be invested in custom CPU ternary kernel optimization.

+-----------------------------------------------------------------------------------+
|                            T81 TERNARY CPU RESEARCH FREEZE                        |
+-----------------------------------------------------------------------------------+
| Subsystem                     | CTest Target                         | Status    |
+-------------------------------+--------------------------------------+-----------+
| experiments/radix_comparison/ | t81_radix_comparison_test            | FROZEN    |
| experiments/packed_ternary/   | t81_packed_ternary_matvec_oracle_test| FROZEN    |
| experiments/packed_ternary/   | t81_packed_ternary_matvec_arm64_test | FROZEN    |
+-----------------------------------------------------------------------------------+

Reproducibility Instructions

1. Build Research Executables:

   cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DT81_BUILD_TESTS=ON
   cmake --build build --target t81_radix_comparison t81_packed_ternary_matvec --parallel 4
   

2. Execute Correctness & Benchmark Harnesses:

   ctest --test-dir build --output-on-failure -R "(radix|packed_ternary)"
   

3. Inspect Machine-Readable Artifacts:
   • build/experiments/radix_comparison/radix_comparison_results.json
   • build/experiments/packed_ternary_matvec/packed_ternary_matvec_results.json

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Phase 4 — Candidate Hypotheses Assessment

To transition T81’s research focus away from incremental CPU kernel micro-optimization, we evaluate five candidate research hypotheses spanning broader mathematical, architectural, and runtime domains.

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Candidate 1: Redundant Signed-Digit (RSD) Multi-Precision Arithmetic Crossover Analysis

• Falsifiable Claim: While RSD representation enables $O(1)$ carry-free parallel addition in hardware, the software overhead of digit-unpacking, carry-transfer logic, and $O(N)$ canonicalization for zero/equality testing on binary ALUs results in higher total latency than standard binary $O(\log N)$ carry-propagate addition for integer widths $N \le 512$ bits.
• Relevant Prior Art: Avizienis (1961), Chow & Robertson (1978), Ercegovac & Lang (2004).
• Existing T81 Evidence: experiments/radix_comparison/ proved Avizienis RSD transfer distance is strictly 1.0 digit, but software 2-step transfer takes $48.1\text{ ns}$ vs $1.1\text{ ns}$ for binary 64-bit ALU add ($43.7\times$ slower).
• Required Experiment: Implement multi-precision (128-bit, 256-bit, 512-bit) SIMD parallel RSD addition vs GMP / binary BigInt addition; measure execution time across operand sizes to find the crossover point where carry-free addition overcomes conversion and normalization overhead.
• Expected Costs: Low (2 weeks engineering, C++ benchmark suite).
• Meaningful Negative Result: If binary SIMD addition remains faster than RSD addition up to 512 bits, software RSD arithmetic has no execution latency advantage for practical BigInt sizes on binary ALUs.
• Stopping Criteria: If binary BigInt addition is $>2\times$ faster at 512 bits, halt further software RSD arithmetic investigation.

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Candidate 2: Hardware Cost Models for Ternary Logic & Memory (ASIC / FPGA vs Binary CMOS)

• Falsifiable Claim: A custom ternary logic cell (gate/memory trit) simulated at the transistor/RTL gate level achieves $>1.5\times$ energy or area efficiency over binary CMOS when evaluating equal information capacity ($\log_2 3 \approx 1.585$ bits/trit), after accounting for multi-threshold voltage degradation and noise margins.
• Relevant Prior Art: Brusentsov (Setun, 1958), Srivastava et al. (CNTFET ternary logic, 2019), Kim et al. (Multi-valued logic, IEEE TCAD 2021).
• Existing T81 Evidence: Ternary_IEEE_Draft.md, theoretical information capacity models ($3^{41} > 2^{64}$).
• Required Experiment: Build Verilog/SystemVerilog gate-level cost model or SPICE simulation of 3-state ternary logic gates (STI - Standard Ternary Inverter, NADI, NORI) vs binary CMOS gates at 7nm/14nm process nodes; measure area ($N M^2$), static/dynamic energy, and SNR noise margins.
• Expected Costs: Medium-High (3-4 weeks engineering, EDA/SPICE simulation tooling required).
• Meaningful Negative Result: If multi-threshold voltage overhead and reduced noise margins degrade energy-delay product (EDP) by $>30\%$ relative to binary CMOS at equivalent throughput, custom ternary hardware logic is economically non-viable vs binary CMOS scaling.
• Stopping Criteria: If EDP of ternary logic gate is higher than binary CMOS gate at equal SNR, halt custom ternary logic hardware claims.

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Candidate 3: Deterministic Execution & Canonical Provenance Verification in Policy-Gated AI Runtimes (RFC-0028 / RFC-0030 / Axion)

• Falsifiable Claim: A policy-gated runtime enforcing strict deterministic math (RFC-0030 CORDIC/Minimax transcendentals) and CanonFS trace-hashing (RFC-0028) can achieve $100\%$ bit-identical cross-platform replay across x86_64, ARM64, and WebAssembly with $<5\%$ execution time overhead compared to non-deterministic host floating-point operations (cmath / native FP).
• Relevant Prior Art: IEEE 754-2019 floating-point standard, WASM determinism profiles, Replay-based state machine replication (Schneider 1990).
• Existing T81 Evidence: PRs #537–#541 (docs/research/consolidation/), Deterministic Trace-JIT (RFC-0028), Deterministic Math Subsystem (RFC-0030).
• Required Experiment: Microbenchmark deterministic CORDIC/Minimax transcendentals (sin, cos, exp, log, softmax) and trace hashing across x86_64 GCC/Clang, ARM64 Apple Clang/GCC, and WASM runtime; verify bit-level equality across 100,000 adversarial inputs; measure throughput penalty vs native libm.
• Expected Costs: Low (2 weeks engineering, C++ microbenchmarks + CTest suite).
• Meaningful Negative Result: If deterministic soft-float transcendentals incur $>20\%$ runtime tax on realistic neural inference workloads, un-gated soft-float math threatens runtime performance, requiring hardware-assisted or table-quantized approximations.
• Stopping Criteria: If cross-platform determinism tax is $<5\%$ on inference traces and 100% bit-identical, validate Option A (Governed Deterministic Runtime) architecture.

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Candidate 4: Ternary-Native Sparse Graph Analytics & Adjacency Representations

• Falsifiable Claim: Graph algorithms (e.g. PageRank, Breadth-First Search, Shortest Path) utilizing packed 2-bit ternary adjacency matrices ($A_{ij} \in {-1, 0, 1}$) achieve $>2\times$ traversal speedup and $4\times$ memory footprint reduction over FP32/INT8 CSR sparse matrix representations on memory-bandwidth-bound graph traversal workloads exceeding L3 cache size.
• Relevant Prior Art: GraphBLAS, Sparse Bit-packed Graph Processing (Dhulipala et al., 2021).
• Existing T81 Evidence: Packed 2-bit memory storage ($0.25$ bytes/trit) verified in experiments/packed_ternary_matvec/.
• Required Experiment: Implement 2-bit packed ternary adjacency matrix graph traversal (SpMV / BFS) vs INT8 / CSR GraphBLAS baselines; benchmark on large power-law graphs (1M-10M nodes) exceeding L3 cache size.
• Expected Costs: Medium (3 weeks engineering, C++ graph benchmark).
• Meaningful Negative Result: If bit manipulation overhead for sparse graph node traversal exceeds memory access savings, packed ternary graph representations offer no runtime speedup over sparse INT8/compressed bitsets.
• Stopping Criteria: If SpMV graph traversal throughput is lower than compressed INT8 CSR, halt software ternary graph algorithm research.

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Candidate 5: Algebraic & Galois Field Representations ($\text{GF}(3^k)$ / Base-81) for Verifiable Storage & Communication

• Falsifiable Claim: Reed-Solomon parity schemes over Galois Field $\text{GF}(3^k)$ (such as $\text{GF}(3^9)$ Base-81) achieve higher computational efficiency and lower encoding/decoding latency than binary $\text{GF}(2^8)$ / $\text{GF}(2^{16})$ for ternary-native provenance storage and CanonFS block verification.
• Relevant Prior Art: Reed & Solomon (1960), McEliece (1977), CanonFS 3+2 RS parity implementation (GF3_9).
• Existing T81 Evidence: CanonFS 3+2 Reed-Solomon parity scheme (GF3_9) in T81 codebase, Base-81 tryte encoding.
• Required Experiment: Microbenchmark $\text{GF}(3^9)$ multiplication (using LUT vs Carry-less multiplication) vs $\text{GF}(2^8)$ / $\text{GF}(2^{16})$ AVX2 SIMD Galois Field instructions (GF2P8AFFINEINVQB); measure block encode/decode throughput in MB/s for CanonFS storage chunks.
• Expected Costs: Low (2 weeks engineering, C++ microbenchmark).
• Meaningful Negative Result: If hardware-accelerated binary Galois Field instructions (GF2P8AFFINEINVQB on x86/ARM) outperform software $\text{GF}(3^9)$ lookup tables by $>5\times$, ternary Galois fields provide no computational performance advantage for storage redundancy.
• Stopping Criteria: If binary GF(2^8) SIMD is $>3\times$ faster than GF(3^9) LUT encoding, restrict Base-81 strictly to human-readable hash string representation rather than underlying Galois Field math.

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Phase 5 — Hypothesis Ranking & Next Experiment Proposal

Candidate Comparative Ranking Matrix

Candidate	Novelty	Feasibility	Scientific Significance	Reproducibility	Implementation Cost	Total Score	Rank
3. Deterministic AI Runtime Verification	High	Very High	High	100% (Bit-Identical)	Low (2 wks)	9.5 / 10	#1 (Selected)
5. Galois Field $\text{GF}(3^9)$ vs $\text{GF}(2^8)$	Medium	High	Medium	100%	Low (2 wks)	7.5 / 10	#2
1. RSD Multi-Precision Crossover	Medium	High	Medium	100%	Low (2 wks)	7.0 / 10	#3
4. Sparse 2-Bit Ternary Graph Analytics	Medium	Medium	Medium	High	Medium (3 wks)	6.5 / 10	#4
2. Transistor-Level Ternary Logic Cost	High	Low	High	Medium	High (4 wks + EDA)	5.5 / 10	#5

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Selected Next Experiment Proposal

Experiment Title

Cross-Platform Bit-Identical Deterministic AI Execution & Trace Provenance Verification (30-Day Bounded Objective)

Objective & Scope

Validate whether T81’s Deterministic Math Subsystem (RFC-0030 CORDIC/Minimax soft-float transcendentals) and Canonical Trace Cache (RFC-0028) can achieve 100% bit-identical execution parity across x86_64, ARM64, and WebAssembly targets under policy-gated pre-side-effect enforcement (Axion), while incurring a $<5\%$ runtime performance tax relative to non-deterministic host libm floating-point operations.

Experimental Design & Test Protocol

1. Target Subsystem: tests/determinism/ and vm/determinism/.
2. Evaluation Workloads:
   • Softmax and LayerNorm activation traces across $100,000$ adversarial floating-point inputs (including subnormals, NaNs, infinities, and extreme exponents).
   • Multi-layer MLP token generation trace ($N=1024$ steps) executed on x86_64 GCC 13, ARM64 Apple Clang 16, and WASM Emscripten.
3. Primary Metrics:
   • Bitwise Hash Parity: CanonHash81(Trace_x86_64) == CanonHash81(Trace_ARM64) == CanonHash81(Trace_WASM).
   • Execution Latency Tax: $\frac{\text{Latency}{\text{DeterministicSoftFloat}} - \text{Latency}{\text{HostLibm}}}{\text{Latency}_{\text{HostLibm}}} \times 100\%$.
4. Stopping Criteria:
   • If cross-platform bitwise parity is achieved with $<5\%$ overhead, validate Option A (Governed Deterministic Runtime) as T81’s core architecture foundation.
   • If overhead exceeds $20\%$, trigger soft-float approximation lookup table optimization.

Note: This proposal outlines the next bounded research objective for the T81 project. No code implementation for this experiment is included in this PR.

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