Repository: T81 Foundation
Research Foundation: Scientific Investigation 05, Investigation 06 (PR #593, PR #594), Hypothesis H-T1
Scope: /experiments/ternary_hardware_feasibility/
This investigation evaluates Hypothesis H-T1 (Bit-Parallel Unpacked Ternary Dot-Product Custom Hardware Overlay) to determine if a hardware datapath optimized for ternary weights $W \in {-1, 0, +1}$ demonstrates a reproducible, measurable efficiency advantage over an equally optimized conventional binary baseline.
Comparing Design C against Design A (a general-purpose INT8 multiplier array) shows a $6.11\times$ gate area reduction at $N=64$, confirming that restricting weights to ${-1, 0, +1}$ yields significant savings by eliminating full 8x8 multiplier trees.
However, when compared against Design B (the critical scientific control: a conventional binary design optimized specifically for weights restricted to ${-1, 0, +1}$), Design C achieves only a $1.098\times$ gate area ratio ($R_{\text{area}} = \text{Area}_B / \text{Area}_C \approx 1.10$).
This falls short of the $1.25\times$ stopping criteria threshold established in Investigation 06 / PR #594. Furthermore, the observed ~10% area difference is an artifact of input encoding interface (unpacked sign/mask bitplanes vs. 2-bit standard binary code) rather than an intrinsic mathematical or arithmetic advantage of ternary logic.
NOT SUPPORTED (for Hypothesis H-T1) — Design C provides no meaningful architectural advantage over an equally optimized binary baseline (Design B) under matched conditions.
Scientific Scope Bounding: The empirical findings reject the specific H-T1 overlay design, but do not reject untested, alternative hardware architectures (e.g. resonant ternary circuits, non-volatile memristive crossbars, or multi-valued physical CMOS cells).
\(Y = \sum_{i=0}^{N-1} W_i X_i\)
For vector length $N = 4096$:
A signed two’s complement integer of width $B$ bits spans $[-2^{B-1}, 2^{B-1} - 1]$.
Thus, 21 bits is the minimum sufficient signed accumulator width for $N = 4096$. All three hardware designs and the independent software reference oracle standardize on a 32-bit signed accumulator ($B_{\text{acc}} = 32$).
An independent reference oracle (reference_oracle.py) was implemented in Python using standard Python integer arithmetic without simulating hardware bitplanes or logic gates. The oracle contains automated generators for directed edge cases (including INT8_MIN negation, zero-heavy vectors, dense vectors, and alternating sign patterns) and deterministic randomized inputs.
Three parameterized Verilog-2012 hardware datapaths were constructed under identical structural assumptions ($N$-element reduction tree, 32-bit exact accumulation):
-X_ext), applies zero-gating, and feeds a 32-bit binary adder reduction tree.Verification was conducted using an automated Icarus Verilog testbench (tb_dot_product.v / run_verification.py) parameterized via root-module parameter overrides (-Ptb_dot_product.N=<N>) across multiple vector lengths $N \in {16, 32, 64}$. All three hardware designs were simulated concurrently against the independent reference oracle across 127 directed and randomized test vectors for each $N$.
VERIFICATION COMPLETE: 127 tests executed, 0 errors per vector length.
Verification PASSED: All designs (A, B, C) match Reference Oracle identically across N=16, 32, 64.
Synthesis was performed using Yosys 0.33 targeting a generic CMOS gate library (abc -g gates). All designs were synthesized across vector lengths $N = 16, 32, 64$ with identical optimization passes (proc; opt; fsm; opt; memory; opt; techmap; opt; abc -g gates; opt).
| Vector Length ($N$) | Design | Raw Gate Cell Count | Estimated Generic Gate Area | Area Ratio vs. Design A ($R_{\text{area, A}}$) | Area Ratio vs. Design B ($R_{\text{area, B}}$) |
|---|---|---|---|---|---|
| $N = 16$ | Design A (General INT8) | 7,715 | 9,050.0 | $1.00\times$ | — |
| Design B (Optimized Binary) | 1,430 | 1,581.5 | $5.72\times$ | $1.00\times$ | |
| Design C (H-T1 Ternary) | 1,188 | 1,436.5 | $6.30\times$ | $1.101\times$ | |
| $N = 32$ | Design A (General INT8) | 15,419 | 18,062.5 | $1.00\times$ | — |
| Design B (Optimized Binary) | 2,927 | 3,240.5 | $5.57\times$ | $1.00\times$ | |
| Design C (H-T1 Ternary) | 2,442 | 2,951.0 | $6.12\times$ | $1.098\times$ | |
| $N = 64$ | Design A (General INT8) | 31,173 | 36,547.5 | $1.00\times$ | — |
| Design B (Optimized Binary) | 5,924 | 6,564.5 | $5.57\times$ | $1.00\times$ | |
| Design C (H-T1 Ternary) | 4,948 | 5,980.5 | $6.11\times$ | $1.098\times$ |
To maintain strict scientific integrity, metrics are categorized into measured physical gate statistics vs unmeasured performance dimensions:
$_NOT_: 0.5, $_AND_: 1.0, $_XOR_: 1.5, $_MUX_: 2.0).UNMEASURED. Static combinational gate area does not incorporate critical path delay or maximum clock frequency ($F_{\text{max}}$). No throughput advantage is claimed.UNMEASURED. Dynamic switching power requires standard cell timing libraries (.lib), place-and-route parasitic RC extraction (SPEF), and toggling activity waveforms (VCD). No energy efficiency advantage is claimed.NOT SUPPORTED.