t81-foundation

RFC-0042: Deterministic Backend Equivalence Contract

Summary

This RFC defines the binding equivalence rules across execution backends in T81.

It establishes:

The purpose of this RFC is to prevent T81 from having multiple backend-specific truths.

Motivation

T81 now exposes multiple execution realizations for the same ternary operations:

RFC-0040 and RFC-0041 formalize optimized execution paths, but they do not yet define the constitutional rule that all optimized paths are merely alternate realizations of a single deterministic computation.

Without this RFC:

Proposal

1. Canonical Oracle

For every governed operation family, T81 MUST define a canonical oracle implementation.

For the current tritwise surface, the canonical oracle is:

For arithmetic surfaces (ADD, SUB, MUL, NEG, DIV, MOD and their type-specific variants), the canonical oracle is defined by RFC-0049 (Canonical Ternary Arithmetic Semantics). The arithmetic oracle specifies:

Backends claiming equivalence on arithmetic surfaces MUST satisfy the RFC-0049 arithmetic oracle, not merely an approximate or locally-defined scalar reference.

The canonical oracle is not required to be the fastest implementation. It is required to be the semantically authoritative implementation.

2. Definition of Backend Equivalence

Two backend implementations are backend-equivalent if, for identical canonical inputs, they produce all of the following identically:

  1. final value bytes
  2. fault class
  3. fault timing at the observable operation boundary
  4. trace-visible operation result
  5. canonical serialization of any produced value

For VM-visible operations, equivalence additionally requires:

  1. identical register-visible result
  2. identical memory-visible result
  3. identical Axion-visible audit meaning
  4. identical CanonHash-relevant trace contribution

“Close enough” is forbidden. Equivalence is exact.

3. Backend Hierarchy

The backend hierarchy is:

  1. scalar
  2. SWAR
  3. SIMD
  4. JIT-lowered native form
  5. future heterogeneous form

Higher tiers may replace lower tiers only if this RFC and the conformance RFC guarantee exact equivalence.

No backend may widen semantics. Backends may only change realization strategy.

4. Allowed Backend Substitutions

A backend substitution is allowed only when:

  1. input encoding is canonical
  2. output encoding is canonical
  3. the backend is within the declared determinism surface
  4. the backend passed the required equivalence corpus for the active architecture
  5. the backend’s dispatch preconditions are deterministic

Examples of allowed substitutions:

Examples of forbidden substitutions:

5. Observable Boundaries

Backend equivalence is evaluated at the deterministic observation boundary, not at internal micro-steps.

For library-level compute surfaces, the observation boundary is:

For VM-visible execution, the observation boundary is:

This allows implementation freedom internally while preserving exact external behavior.

6. Trace Identity Rules

Backend substitution MUST NOT alter the canonical meaning of the trace.

The following are allowed:

The following are forbidden:

If the system records backend selection for diagnostics, that metadata MUST be outside the DCP trace boundary unless separately governed.

7. Dispatch Rules

Dispatch MUST be deterministic.

Dispatch decisions may depend on:

Dispatch decisions may not depend on:

8. Failure Policy

If a backend cannot satisfy the equivalence contract, the system MUST:

  1. fall back to a lower verified backend, or
  2. fail closed with a deterministic error if no verified backend is available

Silent semantic drift is forbidden.

The fallback order SHOULD prefer the nearest lower verified backend.

9. Cross-Architecture Invariant

Supported architectures MUST agree on:

Architecture-specific code generation is allowed only if these invariants remain exact.

10. Scope of This RFC

This RFC governs backend equivalence for execution realization.

It does not, by itself, define:

Those are delegated to companion RFCs.

Acceptance Criteria

This RFC is ready for accepted when all of the following are true:

  1. every governed tritwise backend family declares a canonical oracle
  2. backend dispatch rules are documented for scalar, SWAR, and SIMD paths
  3. trace-visible equivalence rules are explicitly wired into the determinism surface inventory
  4. at least one executable conformance suite enforces scalar vs SWAR vs SIMD equivalence across supported architectures
  5. JIT and future heterogeneous work are explicitly constrained to this contract rather than inventing parallel semantics

Impact

Backward Compatibility

This RFC does not require changing user-facing ternary semantics.

It constrains future implementation freedom by forbidding backend-specific observable behavior.

Performance

No direct performance regression is required.

However, some optimizations may become disallowed if they cannot preserve exact equivalence.

Security

This RFC reduces deterministic-surface drift by making backend substitution governable and testable.

It also narrows the risk of architecture-specific latent divergence.

Alternatives Considered

Treat optimized backends as implementation details

Rejected because the project already exposes backend-governed determinism claims.

Allow value equivalence but not trace equivalence

Rejected because T81 determinism is trace-relevant, not merely result-relevant.

Define equivalence only for current CPU paths

Rejected because JIT and heterogeneous acceleration would reopen the same governance hole later.

References

Implementation Record (2026-03-21)

All acceptance criteria are satisfied as of this date.

AC1 — Canonical oracle declared for every governed backend family: spec/tisc-spec.md §5.2.3 (“Backend Equivalence Contract (RFC-0042)”) defines the canonical oracle table. For tritwise operations the oracle is the scalar trit-by-trit reference implementation. For arithmetic operations (ADD, SUB, MUL, NEG, DIV, MOD) the oracle is the RFC-0049 arithmetic specification (t81::ternary::arith.hpp). No governed backend family is without an explicitly declared oracle.

AC2 — Backend dispatch rules documented for scalar, SWAR, and SIMD: spec/tisc-spec.md §5.2.3 contains the normative dispatch rules table with explicit size thresholds (AVX2_THRESHOLD_BYTES = 64, NEON_TOR_THRESHOLD_BYTES = 64), tail handling strategy (SWAR tail for SIMD kernels), and disabled-path notation (NEON TNot/TAnd set to SIZE_MAX → always falls to SWAR).

AC3 — Trace-visible equivalence wired into the determinism surface inventory: docs/governance/DETERMINISM_SURFACE_REGISTRY.md §5 was updated with two explicit backend equivalence rows:

docs/governance/DETERMINISM_SURFACE_REGISTRY.md §3.1 marks RFC-0042 as accepted.

AC4 — Executable conformance suite enforcing scalar vs SWAR vs SIMD equivalence: Two CI-enforced test targets enforce equivalence across architectures:

Both targets are registered in T81_TEST_TARGETS in CMakeLists.txt and run in ci.yml.

AC5 — JIT and future heterogeneous work explicitly constrained to this contract: docs/developer-guide/internals/jit-equivalence-plan.md was updated with a governance note establishing the JIT as tier 4 in the RFC-0042 backend hierarchy. The note enumerates all five equivalence conditions the JIT must satisfy (register-visible result, memory-visible result, fault class and timing, Axion-visible audit meaning, and CanonHash-relevant trace contribution) and specifies that failure to satisfy any condition MUST trigger interpreter fallback or a deterministic fault — never silent drift.

Promotion framework: This implementation record constitutes the first promotion path that cites RFC-0043 (Deterministic Conformance Validation Framework) as the governing proof model, satisfying RFC-0043 AC5. Backend equivalence for this RFC is proven via RFC-0043 conformance layers 1 (semantic) and 2 (backend equivalence). The cross-platform replay artifacts for x86_64 + AArch64 are defined in docs/governance/DETERMINISM_SURFACE_REGISTRY.md §5.2. Breach classification follows RFC-0043 §6 as codified in docs/governance/FREEZE_ENFORCEMENT.md §4.